Hello,I need to program a multiplexer and a testbench for it. Multiplexer needs to be 4-to-1 using 3 times 2-to-1 multiplexers. 4-to-1 multiplexer inputs need to be 5-bit long and selecters 1 bit long. I need to implement -i think- the output in behavioural, dataflow and structural modelling/design/description stylesAs I understand then output is 5 bit long as well.
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Uut: mux81 port map(. In0 = Rin(0), in1 = Rin(1). 32-bit in0 - in7 signals so you can see the output of your mux change in the sim. It is possible to make simple multiplexer circuits from standard AND and OR gates as we have seen above, but commonly multiplexers/data selectors are available as standard i.c. Packages such as the common TTL 74LS151 8-input to 1 line multiplexer or the TTL 74LS153 Dual 4-input to 1 line multiplexer.
But how can selecter be 1 bit long?Anyway, I have found various examples on the internet. This would do it, basically.
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Said.library IEEE;use IEEE.STDLOGIC1164.all;entity mux8to1 isport(A,B,C,D,E,F,G,H: in bit;S0,S1,S2: in bit;Z: out bit);end mux8to1;architecture bhv of mux8to1 isbeginprocess (A,B,C,D,E,F,G,H,S0,S1,S2) isbeginif (S0 ='0' and S1 = '0' and S2 = '0') thenZ. Said.LIBRARY IEEE;USE IEEE.STDLOGIC1164.ALL;USE IEEE.STDLOGICARITH.ALL;USE IEEE.STDLOGICUNSIGNED.ALL;ENTITY MUX81 ISPORT ( SEL: IN STDLOGICVECTOR(2 DOWNTO 0);A,B,C,D,E,F,G,H:IN STDLOGIC;MUXOUT: OUT STDLOGIC );END MUX81;ARCHITECTURE BEHAVIORAL OF MUX81 ISBEGINPROCESS (SEL,A,B,C,D,E,F,G,H)BEGINCASE SEL ISWHEN '000' = MUXOUT MUXOUT MUXOUT MUXOUT MUXOUT MUXOUT MUXOUT MUXOUT NULL;END CASE;END PROCESS;END BEHAVIORAL.
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